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Figure 7.1. Revision Number Extraction
PID2 ( 0 xE0 0 FFFE8 )
PID3 ( 0 xE0 0 FFFEC )
31:8
7:4
3:0
31:8
7:4
3:0
Rev[ 7:4]
Rev[ 3:0]
The Revision number is to be interpreted according to Table 7.3 (p. 30) .
Table 7.3. Revision Number Interpretation
Revision[7:0]
0x00
0x01
0x02
Revision
A
B
C
7.3.5 Post-reset Behavior
Calibration values are automatically written to registers by the MSC before application code startup. The
values are also available to read from the DI page for later reference by software. Other information
such as the device ID and production date is also stored in the DI page and is readable from software.
7.3.5.1 One Wait-state Access
After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the
MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an
uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software must not select a zero
wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior
is undefined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of
the MSC_READCTRL register must be set to WS1 or WS1SCBTP before the core clock is switched to
the higher frequency clock source.
When changing to a lower frequency, the MODE field of the MSC_READCTRL register must be set to
WS0 or WS0SCBTP only after the frequency transition has completed. If the HFRCO is used, wait until
the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable.
7.3.5.2 Zero Wait-state Access
At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait-
state access greatly improves code execution performance at frequencies from 16 MHz and below.
By default, the Cortex-M3 uses speculative prefetching and If-Then block folding to maximize code
execution performance at the cost of additional flash accesses and energy consumption.
7.3.5.3 Suppressed Conditional Branch Target Prefetch (SCBTP)
MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-
M3 conditional branch target prefetches. Normally, the Cortex-M3 core prefetches both the next
sequential instruction and the instruction at the branch target address when a conditional branch
instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one
extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is
taken or not. To optimize for low energy, the MSC can be configured to cancel these speculative branch
target prefetches. With this configuration, energy consumption is more optimal, as the branch target
instruction fetch is delayed until the branch condition is evaluated.
The performance penalty with this mode enabled is source code dependent, but is normally less than
1% for core frequencies from 16 MHz and below. To enable the mode at frequencies from 16 MHz and
below write WS0SCBTP to the MODE field of the MSC_READCTRL register. For frequencies above 16
MHz, use the WS1SCBTP mode. An increased performance penalty per clock cycle must be expected
2011-04-12 - d0001_Rev1.10
30
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